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FUJITSU SEMICONDUCTOR DATA SHEET
DS07-16704-1E
32-bit Microcontroller
CMOS
FR60 Lite MB91345 Series MB91F345B/F346B
DESCRIPTION
The MB91345 series is the microcontrollers based on 32-bit high-perform RISC-CPU while integrating a variety of I/O resources for embedded control applications which require high-performance, high-speed CPU processing. It is suitable for the embedded control in digital home appliances or audio visual equipment, requiring highperformance CPU processing power. This product compactly integrates a variety of peripheral functions for single chip and is FR60 applicable to fasterspeed application. Note : FR, the abbreviation of FUJITSU RISC controller, is a line of products of FUJITSU Limited.
FEATURE
* FR CPU * 32-bit RISC, load/store architecture, with a five-stage pipeline * Maximum operating frequency : 50 MHz [PLL used : original oscillation 12.5 MHz] * 16-bit fixed length instruction (basic instructions) ; 1 instruction per cycle * Instruction set optimized for embedded applications : Memory-to-Memory transfer, bit manipulation, barrel shift instructions * Instructions adapted for high-level programming languages : Function entry/exit instructions, multiple-register load/store instructions * Register interlock function : Facilitating coding in assembles (Continued)
Be sure to refer to the "Check Sheet" for the latest cautions on development.
"Check Sheet" is seen at the following support page URL : http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html "Check Sheet" lists the minimal requirement items to be checked to prevent problems beforehand in system development.
Copyright(c)2007 FUJITSU LIMITED All rights reserved
MB91345 Series
* On-chip multiplier supported at instruction level Signed 32-bit multiplication : 5 cycles Signed 16-bit multiplication : 3 cycles * Interrupt (PC, PS save) : 6 cycles, 16 priority levels * Harvard architecture allowing program access and data access to be executed simultaneously * Instruction set compatible with FR family * External bus interface * Operating frequency : Max 25 MHz * 24-bit address full output (16 Mbytes area) * 8/16-bit data output * Capable of chip-select signal output for completely independent four areas settable in 64 Kbytes minimum * Support for various memory interfaces : SRAM and ROM/Flash * Basic bus cycle : 2 cycles * Programmable automatic wait cycle generator capable of inserting wait cycles for each area * External wait cycles generated by RDY input * Unused data/address pins can serve for general-purpose I/O * Internal memory Flash MB91F345B MB91F346B 512 Kbytes 1 Mbyte D-bus RAM 24 Kbytes 24 Kbytes F-bus RAM 8 Kbytes 8 Kbytes
* DMAC (DMA Controller) * 5 channels * Two transfer factors (internal peripheral / software) * Addressing mode : 20/24-bit full-address selection (increment/decrement/fixed) * Transfer modes (burst transfer/step transfer/and block transfer) * Selectable transfer data sizes : 8, 16, or 32 bits * Bit search module (for REALOS) Search for the position of the bit I/O-changed first in one word from the MSB * Reload timer : 3 channels (including 1channel for REALOS) * 16-bit timer * The internal clock is optional from 2/8/32 division * Multi function serial interface * 11 channels * Full duplex double buffer * 2 channels out of 11 channels with 16-byte FIFO * Capable of selecting communication mode : asynchronous (Start-Stop synchronous) communication, clock synchronous communication (Max 8.25 Mbps) , I2C* standard mode (Max 100 kbps) , high-speed mode (Max 400 kbps) * Parity on/off selectable * Baud rate generator per channel * Abundant error detection functions are provided (Parity, frame, and overrun) * External clock can be used as transfer clock * ch.0, ch.1, ch.2, and ch.10 is tolerant of 5 V (Continued) 2
MB91345 Series
(Continued) * Interrupt controller * A total of 24 external interrupt lines (external interrupt pins INT23 to INT0) * Interrupt from internal peripheral * Programmable 16 priority levels * Available for wakeup from STOP mode * A/D converter : * 10-bit resolution, 8 channels + 8 channels 2unit * Successive approximation type : Conversion time : min. 1.2 s (at 16 MHz) * Conversion mode (Shingle-shot conversion mode, scan conversion mode) * Startup source (software/external trigger) * PPG timer : up to 16 channels (at 8 bits) * 8/16-bit PPG timer : 8 bits x 16 channels or 16 bits x 8 channels * The internal clock is optional from 1/4/16/64 division * PWC timer : 1 channel 16-bit up counter 1 channel (1 input) * Input capture and output compare : up to 8 channels (ch.0 to ch.3; 16-bit ICU, OCU, ch.4 to ch.7; 32-bit ICU, OCU) * 16-bit free-run counter x 1 channel + 16-bit input capture x 4 channels + 16-bit output compare x 4 channels * 32-bit free-run counter x 1 channel + 32-bit input capture x 4 channels + 32-bit output compare x 4 channels * MIN/MAX/ABS * MIN/MAX/ABS is performed and the result is accumulated and added. * Other interval timer and counter * 8/16-bit up down counter : 8-bit x 4 channels or 16-bit x 2 channels * 16-bit timebase timer/watchdog timer * I/O port * Max 71 ports * Other features * Internal oscillation circuit as a clock source and PLL multiplier * INIT is prepared as a reset terminal * Watchdog timer reset and software reset are also available * Stop and sleep mode supported as low-power-consumption modes * Gear function * Built-in time base timer * Memory patch function * Package : TQFP-100 * CMOS technology (0.18 m) * Power supply voltage : 3.3 V 0.3 V (single power supply) * : Purchase of Fujitsu I2C components conveys a license under the Philips I2C Patent Rights to use, these components in an I2C system provided that the system conforms to the I2C Standard Specification as defined by Philips. 3
MB91345 Series
PIN ASSIGNMENT
(TOP VIEW)
VCC P23/A03/SIN1 P22/A02/SCK0 P21/A01/SOT0 P20/A00/SIN0 P17/D15/ADTRG0 P16/D14/SCK7/ADTRG1 P15/D13/SOT7/TOT2 P14/D12/SIN7/TIN2 P13/D11/SCK6/TOT1 P12/D10/SOT6/TIN1 P11/D09/SIN6/TOT0 P10/D08/SCK5/TIN0 P07/D07/SOT5/INT15 P06/D06/SIN5/INT14 P05/D05/SCK4/INT13 P04/D04/SOT4/INT12 P03/D03/SIN4/INT11 P02/D02/SCK3/INT10 P01/D01/SOT3/INT9 P00/D00/SIN3/INT8 P63/SYSCLK/RT3 P62/RDY/RT2/ADTRG1-2 P61/RT1/PWC0/ADTRG0-2 VCC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
VSS C P24/A04/SOT1 P25/A05/SCK1 P26/A06/SIN2 P27/A07/SOT2 P30/A08/SCK2 P31/A09/AIN0/TOT0-2 P32/A10/BIN0/TOT1-2 P33/A11/ZIN0/TOT2-2 P34/A12/AIN2 P35/A13/BIN2/IC4 P36/A14/ZIN2/IC5 P37/A15/FRCK1 P40/A16/PPG9/INT16 P41/A17/PPGB/INT17 P42/A18/PPGD/INT18 P43/A19/PPGF/INT19 P44/A20/IC0/INT20 P45/A21/IC1/INT21/SIN10 P46/A22/IC2/INT22/SOT10 P47/A23/IC3/INT23/SCK10 VSS X1 X0
VSS P60/RT0 P57/WR1/RT7 P56/WR0/RT6 P55/RD/RT5 P54/AS/RT4 P53/CS3/PPG7 P52/CS2/PPG5 P51/CS1/PPG3 P50/CS0/PPG1 MD2 MD1 MD0 INIT TRST IBREAK ICS2 ICS1 ICS0 ICD3 ICD2 ICD1 ICD0 ICLK VCC
Note : TOTx and TOTx-2 have same function. Also ADTRGx and ADTRGx-2 have same function. Use either of the two depending on the combined resource.
VSS PC2/IC7/SCK9 PC1/IC6/SOT9 PC0/FRCK0/SIN9 PE7/AN15/INT7/SCK8 PE6/AN14/INT6/SOT8 PE5/AN13/INT5/SIN8 PE4/AN12/INT4/PPGE PE3/AN11/INT3/PPGC PE2/AN10/INT2/PPGA PE1/AN9/INT1/PPG8 PE0/AN8/INT0/PPG6 AVSS AVRL AVRH AVCC PD7/AN7/PPG4 PD6/AN6/PPG2 PD5/AN5/ZIN3/PPG0 PD4/AN4/BIN3 PD3/AN3/AIN3 PD2/AN2/ZIN1 PD1/AN1/BIN1 PD0/AN0/AIN1 VCC
(FPT-100P-M18)
4
MB91345 Series
PIN DESCRIPTION
Pin No. 1 2 Pin name VSS C P24 3 A04 SOT1 P25 4 A05 SCK1 P26 5 A06 SIN2 P27 6 A07 SOT2 P30 7 A08 SCK2 P31 8 A09 AIN0 TOT0-2 P32 9 A10 BIN0 TOT1-2 B B B B B B B I/O Circuit type* GND pin Power stabilization capacitance pin General-purpose I/O port Bit 4 of external address bus output pin. Enabled when external bus is effective. Multi function serial 1 serial data output pin General-purpose I/O port. Enabled in single-chip mode. Bit 5 of external address bus output pin. Enabled when external bus is effective. Multi function serial 1 clock I/O pin General-purpose I/O port. Enabled in single-chip mode. Bit 6 of external address bus output pin. Enabled when external bus is effective. Multi function serial 2 serial data input pin General-purpose I/O port. Enabled in single-chip mode. Bit 7 of external address bus output pin. Enabled when external bus is effective. Multi function serial 2 serial data output pin General-purpose I/O port. Enabled in single-chip mode. Bit 8 of external address bus output pin. Enabled when external bus is effective. Multi function serial 2 clock I/O pin General-purpose I/O port. Enabled in single-chip mode. Bit 9 of external address bus output pin. Enabled when external bus is effective. Up down counter input pin Reload timer output pin General-purpose I/O port. Enabled in single-chip mode. Bit 10 of external address bus output pin. Enabled when external bus is effective. Up down counter input pin Reload timer output pin (Continued) Function
5
MB91345 Series
Pin No.
Pin name P33
I/O Circuit type*
Function General-purpose I/O port. Enabled in single-chip mode.
10
A11 ZIN0 TOT2-2 P34
B
Bit 11 of external address bus output pin. Enabled when external bus is effective. Up down counter input pin Reload timer output pin General-purpose I/O port. Enabled in single-chip mode. Bit 12 of external address bus output pin. Enabled when external bus is effective. Up down counter input pin General-purpose I/O port. Enabled in single-chip mode. Bit 13 of external address bus output pin. Enabled when external bus is effective. Up down counter input pin Input capture ICU 4 data sample input pin General-purpose I/O port. Enabled in single-chip mode. Bit 14 of external address bus output pin. Enabled when external bus is effective. Up down counter input pin Input capture ICU 5 data sample input pin General-purpose I/O port. Enabled in single-chip mode. Bit 15 of external address bus output pin. Enabled when external bus is effective. 16-bit free-run timer input pin General-purpose I/O port Bit 16 of external address bus output pin. Enabled when external bus is effective. PPG output pin External interrupt request 16 input pin General-purpose I/O port Bit 17 of external address bus output pin. Enabled when external bus is effective. PPG output pin External interrupt request 17 input pin (Continued)
11
A12 AIN2 P35
B
12
A13 BIN2 IC4 P36
B
13
A14 ZIN2 IC5 P37
B
14
A15 FRCK1 P40
B
15
A16 PPG9 INT16 P41
B
16
A17 PPGB INT17
B
6
MB91345 Series
Pin No.
Pin name P42
I/O Circuit type* General-purpose I/O port B
Function
17
A18 PPGD INT18 P43
Bit 18 of external address bus output pin. Enabled when external bus is effective. PPG output pin External interrupt request 18 input pin General-purpose I/O port Bit 19 of external address bus output pin. Enabled when external bus is effective. PPG output pin External interrupt request 19 input pin General-purpose I/O port Bit 20 of external address bus output pin. Enabled when external bus is effective. Input capture ICU0 data sample input pin External interrupt request 20 input pin General-purpose I/O port Bit 21 of external address bus output pin. Enabled when external bus is effective.
18
A19 PPGF INT19 P44
B
19
A20 IC0 INT20 P45 A21
B
20
IC1 INT21 SIN10 P46 A22
B
Input capture ICU1 data sample input pin External interrupt request 21 input pin Multi function serial 10 serial data input pin General-purpose I/O port Bit 22 of external address bus output pin. Enabled when external bus is effective.
21
IC2 INT22 SOT10 P47 A23
B
Input capture ICU2 data sample input pin External interrupt request 22 input pin Multi function serial 10 serial data output pin General-purpose I/O port Bit 23 of external address bus output pin. Enabled when external bus is effective.
22
IC3 INT23 SCK10
B
Input capture ICU3 data sample input pin External interrupt request 10 input pin Multi function serial 10 clock I/O pin (Continued)
7
MB91345 Series
Pin No. 23 24 25 26 27
Pin name VSS X1 X0 VCC PD0 AN0 AIN1 PD1
I/O Circuit type* A A E GND pin Main clock I/O pin Main clock input pin
Function
Power supply input pin (3.3 V) General-purpose I/O port A/D converter analog input pin Up down counter input pin General-purpose I/O port
28
AN1 BIN1 PD2
E
A/D converter analog input pin Up down counter input pin General-purpose I/O port
29
AN2 ZIN1 PD3
E
A/D converter analog input pin Up down counter input pin General-purpose I/O port
30
AN3 AIN3 PD4
E
A/D converter analog input pin Up down counter input pin General-purpose I/O port
31
AN4 BIN3 PD5 AN5 ZIN3 PPG0 PD6
E
A/D converter analog input pin Up down counter input pin General-purpose I/O port A/D converter analog input pin Up down counter input pin PPG output pin General-purpose I/O port
32
E
33
AN6 PPG2 PD7
E
A/D converter analog input pin PPG output pin General-purpose I/O port
34
AN7 PPG4
E
A/D converter analog input pin PPG output pin (Continued)
8
MB91345 Series
Pin No. 35 36 37 38
Pin name AVCC AVRH AVRL AVSS PE0 AN8 INT0 PPG6 PE1 AN9 INT1 PPG8 PE2 AN10 INT2 PPGA PE3 AN11 INT3 PPGC PE4 AN12 INT4 PPGE PE5 AN13 INT5 SIN8
I/O Circuit type*
Function A/D converter analog power supply input pin A/D converter standard voltage input pin Be sure to turn on/off this power supply when potential of AVRH or more is applied to AVCC. A/D converter standard low voltage input pin A/D converter analog GND pin General-purpose I/O port A/D converter analog input pin External interrupt request 0 input pin PPG output pin General-purpose I/O port A/D converter analog input pin External interrupt request 1 input pin PPG output pin General-purpose I/O port A/D converter analog input pin External interrupt request 2 input pin PPG output pin General-purpose I/O port A/D converter analog input pin External interrupt request 3 input pin PPG output pin General-purpose I/O port A/D converter analog input pin External interrupt request 4 input pin PPG output pin General-purpose I/O port A/D converter analog input pin External interrupt request 5 input pin Multi function serial 8 serial data input pin (Continued)
39
E
40
E
41
E
42
E
43
E
44
E
9
MB91345 Series
Pin No.
Pin name PE6
I/O Circuit type* General-purpose I/O port E
Function
45
AN14 INT6 SOT8 PE7 AN15 INT7 SCK8 PC0
A/D converter analog input pin External interrupt request 6 input pin Multi function serial 8 serial data output pin General-purpose I/O port A/D converter analog input pin External interrupt request 7 input pin Multi function serial 8 clock I/O pin General-purpose I/O port
46
E
47
FRCK0 SIN9 PC1
C
16-bit free-run timer input pin Multi function serial 9 serial data input pin General-purpose I/O port
48
IC6 SOT9 PC2
C
Input capture ICU6 data sample input pin Multi function serial 9 serial data output pin General-purpose I/O port
49 50 51 52 53 54 55 56 57 58 59 60 61 62
IC7 SCK9 VSS VCC ICLK ICD0 ICD1 ICD2 ICD3 ICS0 ICS1 ICS2 IBREAK TRST INIT
C H K K K K J J J I G G
Input capture ICU7 data sample input pin Multi function serial 9 clock I/O pin GND pin Power supply input pin (3.3 V) Development tool clock pin Development tool data pin Development tool data pin Development tool data pin Development tool data pin Development tool status pin Development tool status pin Development tool status pin Development tool break pin Development tool reset pin Initial reset pin (Continued)
10
MB91345 Series
Pin No. 63 64 65 66
Pin name MD0 MD1 MD2 P50 CS0 PPG1 P51
I/O Circuit type* F F F C Mode input pin Mode input pin Mode input pin General-purpose I/O port
Function
External chip select 0. Enabled when external bus is effective. PPG output pin General-purpose I/O port
67
CS1 PPG3 P52
C
External chip select pin. Enabled when external bus is effective. PPG output pin General-purpose I/O port
68
CS2 PPG5 P53
C
External chip select pin. Enabled when external bus is effective. PPG output pin General-purpose I/O port
69
CS3 PPG7 P54
C
External chip select pin. Enabled when external bus is effective. PPG output pin General-purpose I/O port External address strobe output pin. Enabled when external bus is effective. Output compare OCU4 waveform output pin General-purpose I/O port External read strobe output pin. Enabled when external bus is effective. Output compare OCU5 waveform output pin General-purpose I/O port External data bus upper 8-bit write strobe output pin. When external bus is effective, high 8 bits of data during 16-bit access or 8 bits of data during 8-bit access is used as write strobe. Output compare OCU6 waveform output pin (Continued)
70
AS RT4 P55
C
71
RD RT5 P56
C
72
WR0 RT6
D
11
MB91345 Series
Pin No.
Pin name P57
I/O Circuit type* General-purpose I/O port D
Function
73
WR1 RT7
External data bus lower 8-bit write strobe output pin. Enabled when external bus is effective and external bus 16-bit mode is selected. Output compare OCU7 waveform output pin General-purpose I/O port Output compare OCU0 waveform output pin GND pin Power supply input pin (3.3 V) General-purpose I/O port Output compare OCU1 waveform output pin PWC input pin A/D converter trigger input pin General-purpose I/O port External ready input pin. Enabled when both external bus and bus request are effective. Output compare OCU2 waveform output pin A/D converter trigger input pin General-purpose I/O port External clock output pin. Enabled when external bus is effective. Output compare OCU3 waveform output pin General-purpose I/O port Bit 0 of external address/data bus I/O pin. Enabled when external bus is effective. Multi function serial 3 serial data input pin External interrupt request 8 input pin General-purpose I/O port Bit 1 of external address/data bus I/O pin. Enabled when external bus is effective. Multi function serial 3 serial data output pin External interrupt request 9 input pin (Continued)
74 75 76
P60 RT0 VSS VCC P61 RT1 PWC0 ADTRG0-2 P62
C
77
C
78
RDY RT2 ADTRG1-2 P63
C
79
SYSCLK RT3 P00
C
80
D00 SIN3 INT8 P01
C
81
D01 SOT3 INT9
C
12
MB91345 Series
Pin No.
Pin name P02
I/O Circuit type* General-purpose I/O port C
Function
82
D02 SCK3 INT10 P03
Bit 2 of external address/data bus I/O pin. Enabled when external bus is effective. Multi function serial 3 clock I/O pin External interrupt request 10 input pin General-purpose I/O port Bit 3 of external address/data bus I/O pin. Enabled when external bus is effective. Multi function serial 4 serial data input pin External interrupt request 11 input pin General-purpose I/O port Bit 4 of external address/data bus I/O pin. Enabled when external bus is effective. Multi function serial 4 serial data output pin External interrupt request 12 input pin General-purpose I/O port Bit 5 of external address/data bus I/O pin. Enabled when external bus is effective. Multi function serial 4 clock I/O pin External interrupt request 13 input pin General-purpose I/O port Bit 6 of external address/data bus I/O pin. Enabled when external bus is effective. Multi function serial 5 serial data input pin External interrupt request 14 input pin General-purpose I/O port Bit 7 of external address/data bus I/O pin. Enabled when external bus is effective. Multi function serial 5 serial data output pin External interrupt request 12 input pin General-purpose I/O port Bit 8 of external address/data bus I/O pin. Enabled when external bus is effective. Multi function serial 5 clock I/O pin Reload timer event input pin (Continued)
83
D03 SIN4 INT11 P04
C
84
D04 SOT4 INT12 P05
C
85
D05 SCK4 INT13 P06
C
86
D06 SIN5 INT14 P07
C
87
D07 SOT5 INT15 P10
C
88
D08 SCK5 TIN0
C
13
MB91345 Series
Pin No.
Pin name P11
I/O Circuit type* General-purpose I/O port C
Function
89
D09 SIN6 TOT0 P12
Bit 9 of external address/data bus I/O pin. Enabled when external bus is effective. Multi function serial 6 serial data input pin Reload timer output pin General-purpose I/O port Bit 10 of external address/data bus I/O pin. Enabled when external bus is effective. Multi function serial 6 serial data output pin Reload timer event input pin General-purpose I/O port Bit 11 of external address/data bus I/O pin. Enabled when external bus is effective. Multi function serial 6 clock I/O pin Reload timer output pin General-purpose I/O port Bit 12 of external address/data bus I/O pin. Enabled when external bus is effective. Multi function serial 7 serial data input pin Reload timer event input pin General-purpose I/O port Bit 13 of external address/data bus I/O pin. Enabled when external bus is effective. Multi function serial 7 serial data output pin Reload timer output pin General-purpose I/O port Bit 14 of external address/data bus I/O pin. Enabled when external bus is effective. Multi function serial 7 clock I/O pin A/D converter trigger input pin General-purpose I/O port Bit 15 of external address/data bus I/O pin. Enabled when external bus is effective. A/D converter trigger input pin (Continued)
90
D10 SOT6 TIN1 P13
C
91
D11 SCK6 TOT1 P14
C
92
D12 SIN7 TIN2 P15
C
93
D13 SOT7 TOT2 P16
C
94
D14 SCK7 ADTRG1 P17
C
95
D15 ADTRG0
C
14
MB91345 Series
(Continued) Pin No. Pin name P20 96 A00 SIN0 P21 97 A01 SOT0 P22 98 A02 SCK0 P23 99 A03 SIN1 100 VCC C C C C I/O Circuit type* General-purpose I/O port Bit 0 of external address bus output pin. Enabled when external bus is effective. Multi function serial 0 serial data input pin General-purpose I/O port Bit 1 of external address bus output pin. Enabled when external bus is effective. Multi function serial 0 serial data output pin General-purpose I/O port Bit 2 of external address bus output pin. Enabled when external bus is effective. Multi function serial 0 clock I/O pin General-purpose I/O port Bit 3 of external address bus output pin. Enabled when external bus is effective. Multi function serial 1 serial data input pin Power supply input pin (3.3 V) Function
* : For the I/O circuit type, refer to " I/O CIRCUIT TYPE".
15
MB91345 Series
I/O CIRCUIT TYPE
Classification
X1
Circuit type
Remarks Oscillation circuit Feedback resistor X0 : 1 M
Clock input
A
X0
STANDBY CONTROL * CMOS level output IOH = 4 mA * With open drain output control * CMOS level hysteresis input VIH = 0.7 x VCC * With standby control * 5V tolerance
P-ch
Open drain control
N-ch
B
Digital output
Digital input STANDBY CONTROL * CMOS level output IOH = 4 mA * With open drain output control * CMOS level hysteresis input VIH = 0.8 x VCC * With standby control * With pull-up resistor (33 k)
P-ch
P-ch
Open drain control
N-ch
C
Digital output
Digital input STANDBY CONTROL (Continued)
16
MB91345 Series
Classification
Circuit type
P-ch
Remarks * CMOS level output IOH = 4 mA * CMOS level hysteresis input VIH = 0.8 x VCC Standby control provided Without pull-up resistor
Digital output
N-ch
D
Digital output
Digital input STANDBY CONTROL * CMOS level output IOH = 4 mA * With open drain output control * CMOS level hysteresis input VIH = 0.8 x VCC With standby control * With analog input switch * With pull-up resistor (33 k)
P-ch
P-ch
Open drain control
N-ch
Digital output E Analog input CONTROL STANDBY CONTROL
P-ch
Digital input
* CMOS level input * Without standby control
N-ch
F
Digital input (Continued)
17
MB91345 Series
Classification
P-ch
Circuit type
P-ch
Remarks * CMOS hysteresis input * With pull-up resistor
N-ch
G
Digital input CMOS level output
P-ch
Digital output H
N-ch
Digital output
P-ch
* CMOS hysteresis input * With pull-down resistor * Without standby control
I
N-ch
N-ch
Digital input * CMOS level output * CMOS level hysteresis input * Without standby control
P-ch
Digital output
N-ch
J
Digital output
Digital input (Continued)
18
MB91345 Series
(Continued) Classification
Circuit type
P-ch
Remarks * * * * CMOS level output CMOS level hysteresis input Without standby control With pull-down resistor
Digital output
N-ch N-ch
K
Digital output
Digital input
19
MB91345 Series
HANDLING DEVICES
* Preventing Latch-up Latch-up may occur in a COMS IC if a voltage greater than VCC pin, or less than VSS pin is applied to input and output pins, or if an above-rating voltage is applied between VCC pin and VSS pin. If the latch-up occurs, the significantly increases the power supply current and may cause thermal destruction of an element. Thus, When you use a CMOS IC, be very careful not to exceed maximum voltage rating. * Treatment of Unused input pins Do not leave an unused input pin open, since it may cause a malfunction. Thus, use pull-up or pull-down resistor. * About power supply pins If there are multiple VCC pin or VSS pin, from the point of view of device design, pins to be of the same level are connected the inside of the device to prevent such malfunctioning as latch-up. Be sure to connect all of them to the power supply and ground externally for reducing unnecessary radiation, prevent malfunctioning of the strobe signal due to the rise of ground level, and observe the total output current standard. In addition, consideration should be given to connecting VCC/VSS of this device with as low an impedance as possible from the current supply source. Also, we recommend connecting a ceramic capacitor of about 0.1 F as a bypass capacitor between VCC and VSS near this device. * About crystal oscillator circuit Noise near the X0 and X1 pins can cause this device to malfunction. Design the PC board such that X0 and X1 pins, crystal oscillator (or ceramic oscillator) , and bypass capacitor to the ground are placed as near one another as possible. It is strongly recommended to design the PC board artwork with the X0/X1 pins surrounded by a ground plane, as it expects stable operations. Please ask the crystal maker to evaluate the oscillational characteristics of the crystal and this device. * About mode pins (MD0 to MD2) These pins should be connected directly to VCC or VSS pins. To prevent the device erroneously switching to test mode due to noise, design the PC board such that the distance between the mode pins and VCC or VSS pins is as short as possible and the connection impedance is low. * About operation at power-on Be sure to set initialized reset (INIT) with INIT pin immediately after power-on. Immediately after turning on the power, be sure to continue connecting the Low level input to the INIT pin for the stabilization wait time required for oscillator circuit, to secure the stabilization wait time of the oscillator and regulator (For INIT via the INIT pin, the oscillation stabilization wait time setting is initialized to the minimum value) . * About oscillation input at power on When turning on the power, be sure that clock input is maintained until the device is released from the oscillation stabilization wait state. * Note on power-on/off sequences When turning on the power, the output pin may be indeterminate until the internal power supply stabilizes.
20
MB91345 Series
* Note when using external clock In principle, when using external clock, supply a clock to the X0 pin and an opposite-phase clock signal to the X1 pin simultaneously. However in this case, the STOP mode (oscillator stop mode) must not be used, because the X1 pin stops with the "H" output in the STOP mode. At 12.5 MHz or less, the device can be used with the clock signal supplied only to the X0 pin.
Using an External Clock (Normal Method)
X0
X1
MB91345 series [The STOP mode (oscillation stop mode) cannot be used.]
Using an External (enabled at 12.5 MHz or lower)
X0
OPEN X1
MB91345 series
Note : The X1 pin must be designed to have a delay within 15 ns, at 10 MHz, from the signal to the X0 pin. * About C pin MB91345 series has an internal regulator. A bus condenser of 4.7 F or above should be connected to the C pin for the regulator.
C 4.7 F VSS
* About AVCC pin MB91345 series has an internal A/D converter. A condenser of approximately 0.1 F should be connected between the AVCC pin and AVSS pin.
AVCC 0.1 F AVSS
* Treatment of NC pin and OPEN pin The NC and OPEN pins should always be open. 21
MB91345 Series
* Note when not using emulator If evaluation MCU on user system is operated without emulator, each input pin on evaluation MCU connected to the emulator interface on the user system should be handled, as described in the following table. Note that the switch circuit or other function may be required on user system when designing the MCU. Emulator Interface Pin Treatment Evaluation MCU pin name TRST INIT Others
Pin processing Connect to the reset output circuit on the user system. Connect to the reset output circuit on the user system. Open.
22
MB91345 Series
RESTRICTIONS
* Common in the series * Clock control block Take the oscillation stabilization wait time during Low level input to INIT pin. * Bit search module The bit search data register for 0-detection (BSD0) , and bit search data register for 1-detection (BSD1) , and bit search data register for change point detection (BSDC) are only word-accessible. * I/O port Ports are accessed only in bytes. * Low power consumption mode * To enter the standby mode, use the synchronous standby mode (set with the SYNCS bit as bit8 in TBCR, or timebase counter control register) and be sure to use the following sequence : (ldi #value_of_standby, r0) (ldi #_STCR, r12) stb r0, @r12 // set STOP/SLEEP bit ldub @r12, r0 // Must read STCR ldub @r12, r0 // after reading, go into standby mode nop // Must insert NOP *5 nop nop nop nop * Please do not do the following when the monitor debugger is used * Setting of the break point to the above instructions. * Execution of the single-stepping for the above instructions.
23
MB91345 Series
* Notes on the PS register As the PS register is processed by some instructions in advance, exception handling below may cause the interrupt handling routine to break when the debugger is used or the display contents of flags in the PS register to be updated. In either case, the operations before and after an EIT are performed as specified as the device is designed such that the recovery from the EIT is followed by correct re-processing. * The instruction just before the DIV0U/DIV0S instruction may cause the following operation, if a user interrupt or NMI occurs, single-stepping is performed or a break is caused by a data event or emulator menu : (1) The D0 and D1 flags are updated in advance. (2) An EIT handling routine (user interrupt, NMI, or emulator) is executed. (3) Upon returning from the EIT, the DIV0U/DIV0S instruction is executed and the D0 and D1 flags are updated to the same values as shown in (1) . * If the ORCCR/STILM/MOV Ri and PS instructions are executed to enable interruptions when a user interrupt or NMI trigger even has occurred, the following operations are performed. (1) The PS register is updated in advance. (2) An EIT handling routine (user interrupt, NMI, or emulator) is executed. (3) Upon returning from the EIT, the instructions shown above are executed and the PS register is updated to the same value as shown in (1) . * About watchdog timer MB91345 series has an internal function called "watchdog timer". This function monitors a program to perform the reset defer operation within a certain period of time. The watchdog timer resets the CPU if the program runs out of controls and the reset defer operation is not executed. Thus, once enabled, the watchdog timer will be up and running until it resets the CPU. However, with one exception, the watchdog timer automatically defers a reset timing under the condition in which the CPU stops program execution. Refer to the section describing the watchdog timer functions for the exceptional condition. If the system runs out of control and develops the above condition, a watchdog reset may not be generated. In that case, please reset (INIT) from external INIT terminal. * Note on using the A/D converter MB91345 series has an internal A/D converter. The AVCC pin should not be supplied with higher voltage than VCC pin. * Software reset in synchronous mode When using the software reset in the synchronous mode, the following two conditions should be satisfied before setting "0" to the SRST bit in STCR (Standby control register) . * Set the interrupt enable flag (I-Flag) to interrupt disable (I-Flag = 0) . * Do not use NMI. * Debug control when using ICE * Single-stepping of the RETI instruction If an interrupt occurs frequently during single stepping, only the relevant interrupt processing routine is executed repeatedly after single-stepping RETI. This will prevent the main routine and low-interrupt-level programs from being executed. Do not single-step the RETI instruction for escape. When the debugging of the relevant interrupt routine no longer requires, perform debugging with that interrupt disabled. * About operand break Do not apply a data event break to access to the area containing the address of a stack pointer.
24
MB91345 Series
* Execution of an unused area of Flash memory Accidently if an unused area (data at 0XFFFF) of Flash memory is executed in an instruction, no break can be accepted. To avoid this, it is recommended to use the code event address mask feature of the debugger to break at instruction access to the unused area. * Interrupt handler for NMI request (tool) Add the following program to the interrupt handler to prevent the device from malfunctioning when the source flag is set accidentlly with no ICE connected, for example, due to noise to the DSU pin, which is to be set only at the break request of the ICE. can be used normally with this program added. Add place : Next interrupt handler Interrupt source : NMI request (tool) Interrupt number : 13 (decimal) , 0D (hexadecimal) Offset : 3C8H TBR default address : 000FFFC8H Add program STM (R0, R1) LDI #0B00H, R0 LDI #0, R1 STB R1, @R0 LDM (R0, R1) RETI ; Clear the break source register ; 0B00H is the address of DSU break source register
25
MB91345 Series
BLOCK DIAGRAM
FR60 Lite CPU core
Operating macro for absolute value Bit search
RAM 24 Kbytes (data)
32
32
DMAC 5 channels
Flash 512 Kbytes RAM 8 Kbytes
32
Bus Converter
32
D15 ~ D00 A23 ~ A00
X0, X1 MD2 ~ MD0 INIT
32 16 Adapter Clock control
16
External memory I/F
RD, WR1, WR0 CS3 ~ CS0 RDY SYSCLK
PORT 3 channels 16-bit Reload timer 16-bit Free-run timer 4 channels 16-bit Input capture
4 channels 16-bit Output compare
PORT
Interrupt controller
INT23 ~ INT0 SIN10 ~ SIN0 SOT10 ~ SOT0 SCK10 ~ SCK0 AN7 ~ AN0 ADTRG0, ADTRG0-2 AVRH, AVCC AVSS/AVRL ADTRG1, ADTRG1-2 AN15 ~ AN8 AIN3 ~ AIN0, BIN3 ~ BIN0, ZIN3 ~ ZIN0
TOT2 ~ TOT0 TIN2 ~ TIN0 FRCK0
24 channels External interrupt
11 channels Multi function serial interface. (including 2 channels with built-in FIFO)
IC3 ~ IC0
8 channels x 1 unit 10-bit A/D Converter 8 channels x 1 unit 10-bit A/D Converter
2 channels 8/16-bit up down counter
RT3 ~ RT0
32-bit Free-run timer 4 channels 32-bit Input capture
4 channels 32-bit Output compare
FRCK1
IC7 ~ IC4
RT7 ~ RT4
PPGF ~ PPGF0
16 channels 8/16-bit PPG
26
MB91345 Series
CPU AND CONTROL UNIT
The FR family CPU is a line of high-performance cores based on a RISC architecture while incorporating advanced instructions for embedded controller applications.
1. Features
* RISC architecture adopted. Basic instructions : Executed at 1 instruction per cycle * 32-bit architecture General purpose registers : 32 bit x 16 * 4G bytes of linear memory space * Multiplier integrated. 32-bit x 32-bit multiplication : 5 cycles. 16-bit x 16-bit multiplication : 3 cycles * Enhanced interrupt servicing. High-speed response (6 cycles) . Multi-level interrupts support. Level mask feature (16 levels) * Enhanced I/O manipulation instructions. Memory-to-memory transfer instructions Bit manipulation instructions * High code efficiency. Basic instruction word length : 16-bit * Low-power consumption. Sleep mode / stop mode * Gear function
27
MB91345 Series
2. Internal architecture
The FR-family CPU has a Harvard architecture in which the instruction bus and data buses are separated. The 32-bit16-bit bus converter is connected to a 32-bit bus (F-bus) , providing an interface between the CPU and peripheral resources. The HarvardPrinceton bus converter is connected to both of the I-bus and D-bus, providing an interface between the CPU and the bus controller.
FR CPU D-bus I-bus
32 I address 32 I data D address 32 Princeton bus converter External data 16 Harvard External address 24
Data RAM
D data
32
Address 32-bit 16-bit bus converter Data
32
32
16
R-bus
F-bus
Peripherals resource
Internal I/O
bus controller
28
MB91345 Series
3. Programming model
Basic programming model 32-bit Initial Value
R0 R1 XXXX XXXXH
GENERAL PURPOSE REGISTERS
R12 R13 R14 R15
AC FP SP
XXXX XXXXH 0000 0000H
Program counter program status Table base register Return pointer System stack pointer User stack pointer
PC PS TBR RP SSP USP
ILM
SCR
CCR
Multiply and divide result MDH register
MDL
29
MB91345 Series
4. Register
General purpose registers
32 bit Initial Value
R0 R1 XXXX XXXXH
R12 R13 R14 R15
AC FP SP
XXXX XXXXH 0000 0000H
Registers R0 to R15 are general purpose registers. The registers are used as the accumulator and memory access pointers for CPU operations. Of these 16 registers, the registers listed below are intended for special applications, for which some instructions are enhanced. R13 : Virtual accumulator R14 : Frame pointer R15 : Stack pointer The initial values of R0 to R14 after a reset are indeterminate. R15 is initialized to 00000000H (SSP value) . * PS (Program Status) This register holds the program status and is divided into the ILM, SCR, and CCR. All of undefined bits are reserved bits. Reading these bits always returns "0". Writing to them has no effect.
bit31 bit20 bit16 bit10 bit8 bit7 bit0
ILM
SCR
CCR
PS
* CCR (Condition Code Register)
bit7 bit6 bit5 S bit4 I bit3 N bit2 Z bit1 V bit0 C
Initial Value - - 00XXXXB
S : Stack flag. Cleared to "0" at a reset. 30
MB91345 Series
I N Z V C : Interrupt Enable flag. Cleared to "0" at a reset. : Negative flag. Initial State at a reset is unspecified. : Zero flag. Initial State at a reset is unspecified. : Overflow flag. Initial State at a reset is unspecified. : Carry flag. Initial State at a reset is unspecified.
* SCR (System Condition code Register)
bit10 bit9 D1 D0 bit8 T
Initial Value XX0B
Flag for step dividing Stores intermediate data for stepwise multiplication operations. Step trace trap flag A flag specifying whether the step trace trap function is enabled or not. Emulator uses step trace trap function. The function cannot be used by the user program when using the emulator. * ILM (Interrupt Level Mask Register)
bit20 bit19 bit18 bit17 bit16 ILM4 ILM3 ILM2 ILM1 ILM0
Initial Value 01111B
This register stores the interrupt level mask value. The value in the ILM register is used as the level mask. Initialized to "15" (01111B) by a reset. * PC (Program Counter)
bit31 bit0
Initial Value XXXXXXXXH
The program counter contains the address of the instruction currently being executed. The initial value after a reset is indeterminate. * TBR (Table Base Register)
bit31 bit0
Initial Value 0 0 0 FFC0 0H
The table base register contains the start address of the vector table used for servicing EIT events. The initial value after a reset is 000FFC00H.
31
MB91345 Series
* RP (Return Pointer)
bit31 bit0
Initial Value XXXXXXXXH
The return pointer contains the address to which to return from a subroutine. When the CALL instruction is executed, the value in the PC is transferred to the RP. When the RET instruction is executed, the value in the RP is transferred to the PC. The initial value after a reset is indeterminate. * SSP (System Stack Pointer)
bit31 bit0
Initial Value 0 0 0 0 0 0 0 0H
The SSP is the system stack pointer and functions as R15 when the S flag is "0". The SSP can be explicitly specified. The SSP is also used as the stack pointer that specifies the stack for saving the PS and PC when an EIT event occurs. The initial value after a reset is 00000000H. * USP (User Stack Pointer)
bit31 bit0
Initial Value XXXXXXXXH
The USP is the user stack pointer and functions as R15 when the S flag is "1". The USP can be explicitly specified. The initial value after a reset is indeterminate. This pointer cannot be used by the RETI instruction. * MDH, MDL (Multiply and Divide register)
bit31 bit0
MDH MDL
Multiplication and division result register These registers hold the results of a multiplication or division. Each of them is 32-bit long. The initial value after a reset is indeterminate.
32
MB91345 Series
MODE SETTING
In the FR family, operation mode is set by the mode setting pins (MD2, MD1, MD0) and the mode register (MODR) .
1. Mode pins
They are three pins of MD2, MD1 and MD0, and specify the contents of the mode vector fetch. Mode pins Mode name Reset vector Access area MD2 MD1 MD0 0 0 0 Internal ROM mode vector Internal
Note : In the FR family, external mode vector fetch by multiplex bus is not supported.
2. Mode register (MODR)
The data that are written in the mode register by mode vector fetch is called mode data. After the mode register (MODR) is set, it operates in the operation mode set by this register. The mode register is set by all reset source. And Mode data is not written in by the user program. Note : Conventionally, the address (0000 07FFH) of the mode register for the FR family holds nothing. Details of the mode register MODR 0007FDH
bit7 0 bit6 0 bit5 0 bit4 0 bit3 0 bit2 ROMA bit1 WTH1 bit0 WTH0
Initial Value XXXXXXXXB
Operation mode setting bits
[bit7 to bit3] Reserved bits Be sure to set these bits to "00000B". Setting the bits to any value other than "00000B" may result in an unpredictable operation . [bit2] ROMA (Internal ROM enable bit) This bit sets to make internal F-bus RAM and F-bus ROM areas valid or not. ROMA 0 1 Function External ROM mode Remarks Embedded F-bus RAM becomes valid, and internal ROM area (50000H to 100000H) becomes external area.
Internal ROM mode Embedded F-bus RAM and F-bus ROM become valid.
33
MB91345 Series
[bit1, bit0] WTH1, WTH0 (Bus width specifying bits) These bits specify bus widths for the external bus mode. In case of the external bus mode, this value is set in the DBW0 bit of ACR0 (CS0 area) . WTH1 0 0 1 1 WTH0 0 1 0 1 Single chip mode 8-bit bus width 16-bit bus width Function Remarks External bus mode External bus mode Setting disabled Single chip mode
34
MB91345 Series
MEMORY SPACE
1. Memory Space
The FR family has 4 Gbytes of logical address space (232 addresses) linearly accessible to the CPU . * Direct Addressing Areas The following address space areas are used as I/O areas. These areas are called direct addressing areas, in which the address of an operand can be specified directly during an instruction. The direct area varies depending on the size of data to be accessed as follows : byte data access word data access : 000H to 0FFH : 000H to 3FFH half word data access : 000H to 1FFH
2. Memory Map (MB91F345B/F346B)
Single chip mode
0000 0000H I/O 0000 0400H I/O 0001 0000H I/O I/O
Internal ROM external bus mode Direct addressing area Refer to "3. I/O Map"
Access prohibited
0003 E000H
Access prohibited
Internal RAM 8 Kbytes (Data/instruction) Internal RAM 24 Kbytes (Data)
0004 0000H 0004 6000H 0005 0000H 0008 0000H
Internal RAM 8 Kbytes (Data/instruction) Internal RAM 24 Kbytes (Data)
Access prohibited
Internal Flash* 512 Kbytes
Access prohibited
External area
Internal Flash* 512 Kbytes
Access prohibited
0010 0000H 0020 0000H FFFF FFFFH
Access prohibited
External area
* : Internal Flash area of MB91F346B is 0008 0000H to 0018 0000H (1 Mbyte.)
35
MB91345 Series
I/O MAP
The following table shows the correspondence between the memory space area and each register of the peripheral resource. [How to read the table] Address 000000H Register +0 +1 +2 +3 PDR0 [R/W] B PDR1 [R/W] B PDR2 [R/W] B PDR3 [R/W] B XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX Block T-unit Port Data Register
Read/write attribute, Access unit (B : Byte, H : Half Word, W : Word) Initial value after a reset Register name (First-column register at address 4n; second-column register at address 4n + 1...) Location of left-most register (When using word access, the register in column 1 is in the MSB side of the data.) Note : Initial values of register bits are represented as follows : "1" : Initial value is "1". "0" : Initial value is "0". "X" : Initial value is "indeterminate". "-" : No physical register at this location Access is barred with an undefined data access attribute.
36
MB91345 Series
Address 000000H 000004H 000008H 00000CH 000010H to 00001CH 000020H 000024H 000028H 00002CH 000030H 000034H 000038H 00003CH 000040H 000044H 000048H 00004CH 000050H 000054H
Register 0 1 2 3 PDR0 [R/W] B, H PDR1 [R/W] B, H PDR2 [R/W] B, H PDR3 [R/W] B, H XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX PDR4 [R/W] B, H PDR5 [R/W] B, H PDR6 [R/W] B, H XXXXXXXX XXXXXXXX ----XXXX PDRC [R/W] B, H PDRD [R/W] B, H PDRE [R/W] B, H -----XXX XXXXXXXX XXXXXXXX ADCS01 [R/W] 00000000 ADCS00 [R, R/W] 00000000 ADERH0 [R/W] 11111111 ADCR0 [R] ------XX XXXXXXXX ADSCH0 [R/W] 0---0000 ADECH0 [R/W] ----0000
Block
Port Data Registers
Reserved
A/D converter 0
ADCT0 [R/W] 00010000 00101100 ADCR0M [R] ------XX XXXXXXXX ADCS11 [R/W] 00000000 ADCS10 [R, R/W] 00000000
ADCR1M [R] ------XX XXXXXXXX ADERH1 [R/W] 11111111 ADCR1 [R] ------XX XXXXXXXX ADSCH1 [R/W] 0----000 ADECH1 [R/W] -----000
AD mirror data register
A/D converter 1
ADCT1 [R/W] 00010000 00101100 EIRR0 [R/W] 00000000 DICR [R/W] 00000000 ENIR0 [R/W] 00000000 HRCL [R, R/W] 0--11111
Reserved ELVR0 [R/W] 00000000 00000000 TMR0 [R] XXXXXXXX XXXXXXXX TMCSR0 [R, RW] 00000000 00000000 TMR1 [R] XXXXXXXX XXXXXXXX TMCSR1 [R, RW] 00000000 00000000 External interrupt INT 0 to INT7 DLY / I-unit
TMRLR0 [W] XXXXXXXX XXXXXXXX TMRLR1 [W] XXXXXXXX XXXXXXXX
Reload Timer 0
Reload Timer 1
(Continued)
37
MB91345 Series
Address 000058H 00005CH
Register 0 1 2 3 TMRLR2 [W] XXXXXXXX XXXXXXXX SCR0/IBCR0 [R, R/W] * SMR0 [W, R/W] * TMR2 [R] XXXXXXXX XXXXXXXX TMCSR2 [R, RW] 00000000 00000000 SSR0 [R, R/W] * BGR01 [R/W] * FCR01 [R/W] * SSR1 [R, R/W] * BGR11 [R/W] * FCR11 [R/W] * SSR2 [R, R/W] * BGR21 [R/W] * SCR3/IBCR3 [R, R/W] * SMR3 [W, R/W] * SSR3 [R, R/W] * BGR31 [R/W] * ESCR3/IBSR3 [R/W] * BGR30 [R/W] * ESCR2/IBSR2 [R/W] * BGR20 [R/W] * ESCR1/IBSR1 [R/W] * BGR10 [R/W] * FCR10 [R/W] * ESCR0/IBSR0 [R/W] * BGR00 [R/W] * FCR00 [R/W] *
Block
Reload Timer 2
000060H
000064H 000068H 00006CH
RDR0/TDR0 [R/W] * ISMK0 [R/W] * FBYTE02 [R/W] * SCR1/IBCR1 [R, R/W] * IBSA [R/W] * FBYTE01 [R/W] * SMR1 [W, R/W] *
Multi function Serial Interface 0 FIFO 0
000070H
000074H 000078H 00007CH
RDR1/TDR1 [R/W] * ISMK1 [R/W] * FBYTE12 [R/W] * SCR2/IBCR2 [R, R/W] * IBSA1 [R/W] * FBYTE11 [R/W] * SMR2 [W, R/W] *
Multi function Serial Interface 1 FIFO 1
000080H
000084H 000088H 00008CH 000090H
RDR2/TDR2 [R/W] * ISMK2 [R/W] * IBSA2 [R/W] *
Multi function Serial Interface 2
000094H 000098H 00009CH
RDR3/TDR3 [R/W] * ISMK3 [R/W] * IBSA3 [R/W] *
Multi function Serial Interface 3
(Continued)
38
MB91345 Series
Address
Register 0 SCR4/IBCR4 [R, R/W] * 1 SMR4 [W, R/W] * 2 SSR4 [R, R/W] * BGR41 [R/W] * SCR5/IBCR5 [R, R/W] * SMR5 [W, R/W] * SSR5 [R, R/W] * BGR51 [R/W] * EIRR1 [R/W] 00000000 EIRR2 [R/W] 00000000 ENIR1 [R/W] 00000000 ENIR2 [R/W] 00000000 CPCLRB/CPCLR [R/W] H 11111111 11111111 TCCSH [R/W] B 00000000 TCCSL [R/W] B 01000000 IPCPH0/IPCPL0 [R] XXXXXXXX XXXXXXXX IPCPH2/IPCPL2 [R] XXXXXXXX XXXXXXXX ICSH01 [R/W] ------00 ICSL01 [R/W] 00000000 IPCPH1/IPCPL1 [R] XXXXXXXX XXXXXXXX IPCPH3/IPCPL3 [R] XXXXXXXX XXXXXXXX ICSH23 [R/W] ------00 ICSL23 [R/W] 00000000 TCDT [R/W] H 00000000 00000000 ELVR1 [R/W] 00000000 00000000 ELVR2 [R/W] 00000000 00000000 ESCR5/IBSR5 [R/W] * BGR50 [R/W] * 3 ESCR4/IBSR4 [R/W] * BGR40 [R/W] *
Block
0000A0H
0000A4H 0000A8H 0000ACH 0000B0H
RDR4/TDR4 [R/W] * ISMK4 [R/W] * IBSA4 [R/W] *
Multi function Serial Interface 4
0000B4H 0000B8H 0000BCH 0000C0H 0000C4H 0000C8H to 0000CCH 0000D0H 0000D4H 0000D8H 0000DCH 0000E0H 0000E4H 0000E8H 0000ECH
RDR5/TDR5 [R/W] * ISMK5 [R/W] * IBSA5 [R/W] *
Multi function Serial Interface 5
External interrupt INT 8 to INT15 External interrupt INT 16 to INT 23 Reserved
16-bit Free Run Timer 0 Reserved
16-bit Input Capture
OCCPH0/OCCPL0 [R/W] XXXXXXXX XXXXXXXX OCCPH2/OCCPL2 [R/W] XXXXXXXX XXXXXXXX OCS01 [R/W] 11101100 00001100
OCCPH1/OCCPL1 [R/W] XXXXXXXX XXXXXXXX OCCPH3/OCCPL3 [R/W] XXXXXXXX XXXXXXXX OCS23 [R/W] 11101100 00001100
Output Compare 0, 1 Output Compare 2, 3 Output Compare 0 to 3 Control (Continued) 39
0000F0H
MB91345 Series
Address 0000F4H 0000F8H
Register 0 OCMOD [R/W] B 00000000 PWCSR0 [R/W, R] B, H, W 0000000X 00000000 PRLH0 [R/W] B, H, W XXXXXXXX PRLH2 [R/W] B, H, W XXXXXXXX PPGC0 [R/W] B, H, W 0000000X PRLH4 [R/W] B, H, W XXXXXXXX PRLH6 [R/W] B, H, W XXXXXXXX PPGC4 [R/W] B, H, W 0000000X PRLH8 [R/W] B, H, W XXXXXXXX PRLHA [R/W] B, H, W XXXXXXXX PPGC8 [R/W] B, H, W 0000000X PRLHC [R/W] B, H, W XXXXXXXX PRLHE [R/W] B, H, W XXXXXXXX PPGCC [R/W] B, H, W 0000000X PDIVR0 [R/W] B, H, W XXXXX000 PRLL0 [R/W] B, H, W XXXXXXXX PRLL2 [R/W] B, H, W XXXXXXXX PPGC1 [R/W] B, H, W 0000000X PRLL4 [R/W] B, H, W XXXXXXXX PRLL6 [R/W] B, H, W XXXXXXXX PPGC5 [R/W] B, H, W 0000000X PRLL8 [R/W] B, H, W XXXXXXXX PRLLA [R/W] B, H, W XXXXXXXX PPGC9 [R/W] B, H, W 0000000X PRLLC [R/W] B, H, W XXXXXXXX PRLLE [R/W] B, H, W XXXXXXXX PPGCD [R/W] B, H, W 0000000X PRLH1 [R/W] B, H, W XXXXXXXX PRLH3 [R/W] B, H, W XXXXXXXX PPGC2 [R/W] B, H, W 0000000X PRLH5 [R/W] B, H, W XXXXXXXX PRLH7 [R/W] B, H, W XXXXXXXX PPGC6 [R/W] B, H, W 0000000X PRLH9 [R/W] B, H, W XXXXXXXX PRLHB [R/W] B, H, W XXXXXXXX PPGCA [R/W] B, H, W 0000000X PRLHD [R/W] B, H, W XXXXXXXX PRLHF [R/W] B, H, W XXXXXXXX PPGCE [R/W] B, H, W 0000000X 1 2 PWCR0 [R] H, W 00000000 00000000 3
Block Output Compare Mode Select
PWC PRLL1 [R/W] B, H, W XXXXXXXX PRLL3 [R/W] B, H, W XXXXXXXX PPGC3 [R/W] B, H, W 0000000X PRLL5 [R/W] B, H, W XXXXXXXX PRLL7 [R/W] B, H, W XXXXXXXX PPGC7 [R/W] B, H, W 0000000X PRLL9 [R/W] B, H, W XXXXXXXX PRLLB [R/W] B, H, W XXXXXXXX PPGCB [R/W] B, H, W 0000000X PRLLD [R/W] B, H, W XXXXXXXX PRLLF [R/W] B, H, W XXXXXXXX PPGCF [R/W] B, H, W 0000000X (Continued)
0000FCH
000100H
000104H
000108H
00010CH
000110H
000114H
PPG 0 to PPG F
000118H
00011CH
000120H
000124H
000128H
00012CH
40
MB91345 Series
Address
Register 0 1 2 CPCLRB/CPCLR [R/W] W 11111111 11111111 11111111 11111111 TCDT [R/W] W 00000000 00000000 00000000 00000000 TCCSH [R/W] B 00000000 TCCSL [R/W] B 01000000 3 PPGGATEC [R/W] B XXXXXX00
Block
000130H
PPGTRG [R/W] B, H, W 00000000 00000000 PPGREVC [R/W] B, H, W 00000000 00000000
PPG 0-F
000134H 000138H to 00014CH 000150H 000154H 000158H 00015CH 000160H 000164H 000168H 00016CH 000170H 000174H 000178H 00017CH 000180H 000184H
Reserved
32 bit Free Run Timer 0
IPCP4 [R] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX IPCP5 [R] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX IPCP6 [R] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX IPCP7 [R] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX ICS45 [R/W] 00000000 ICS67 [R/W] 00000000 32 bit Input Capture Unit 4 to 7
OCCP4 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX OCCP5 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX OCCP6 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX OCCP7 [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX OCS45 [R/W] 11101100 00001100 RCRH1 [W] B, H 00000000 CCRH0 [R/W] B, H 00000000 CCRH1 [R/W] B, H 00000000 RCRL0 [W] B, H 00000000 CCRL0 [R/W] B, H 00000000 CCRL1 [R/W] B, H 00000000 OCS67 [R/W] 11101100 00001100 UDCR1 [R] B, H 00000000 UDCR0 [R] B, H 00000000 CSR0 [R/W] B 00000000 CSR1 [R/W] B 00000000 (Continued) 41 Up/Down Counter 0, 1 32 bit Output Compare 4 to 7
000188H
00018CH
MB91345 Series
Address 000190H 000194H
Register 0 RCRH3 [W] B, H 00000000 CCRH2 [R/W] B, H 00000000 CCRH3 [R/W] B, H 00000000 1 RCRL2 [W] B, H 00000000 CCRL2 [R/W] B, H 00000000 CCRL3 [R/W] B, H 00000000 SCR6/IBCR6 [R, R/W] * SMR6 [W, R/W] * SSR6 [R, R/W] * BGR61 [R/W] * SCR7/IBCR7 [R, R/W] * SMR7 [W, R/W] * SSR7 [R, R/W] * BGR71 [R/W] * SCR8/IBCR8 [R, R/W] * SMR8 [W, R/W] * SSR8 [R, R/W] * BGR81 [R/W] * ESCR8/IBSR8 [R/W] * BGR80 [R/W] * ESCR7/IBSR7 [R/W] * BGR70 [R/W] * ESCR6/IBSR6 [R/W] * BGR60 [R/W] * UDCR3 [R] B, H 00000000 UDCR2 [R] B, H 00000000 CSR2 [R/W] B 00000000 CSR3 [R/W] B 00000000 2 3
Block Reserved
000198H
Up/Down Counter 2, 3
00019CH 0001A0H to 0001ACH 0001B0H
Reserved
0001B4H 0001B8H 0001BCH 0001C0H
RDR6/TDR6 [R/W] * ISMK6 [R/W] * IBSA6 [R/W] *
Multi function Serial Interface 6
0001C4H 0001C8H 0001CCH 0001D0H
RDR7/TDR7 [R/W] * ISMK7 [R/W] * IBSA7 [R/W] *
Multi function Serial Interface 7
0001D4H 0001D8H 0001DCH
RDR8/TDR8 [R/W] * ISMK8 [R/W] * IBSA8 [R/W] *
Multi function Serial Interface 8
(Continued)
42
MB91345 Series
Address
Register 0 SCR9/IBCR9 [R, R/W] * 1 SMR9 [W, R/W] * 2 SSR9 [R, R/W] * BGR91 [R/W] * SCRA/IBCRA [R, R/W] * SMRA [W, R/W] * SSRA [R, R/W] * BGRA1 [R/W] * DMACA0 [R/W] 00000000 00000000 00000000 00000000 DMACB0 [R/W] 00000000 00000000 00000000 00000000 DMACA1 [R/W] 00000000 00000000 00000000 00000000 DMACB1 [R/W] 00000000 00000000 00000000 00000000 DMACA2 [R/W] 00000000 00000000 00000000 00000000 DMACB2 [R/W] 00000000 00000000 00000000 00000000 DMACA3 [R/W] 00000000 00000000 00000000 00000000 DMACB3 [R/W] 00000000 00000000 00000000 00000000 DMACA4 [R/W] 00000000 00000000 00000000 00000000 DMACB4 [R/W] 00000000 00000000 00000000 00000000 DMACR [R/W] 0XX00000 XXXXXXXX XXXXXXXX XXXXXXXX ESCRA/IBSRA [R/W] * BGRA0 [R/W] * 3 ESCR9/IBSR9 [R/W] * BGR90 [R/W] *
Block
0001E0H
0001E4H 0001E8H 0001ECH 0001F0H
RDR9/TDR9 [R/W] * ISMK9 [R/W] * IBSA9 [R/W] *
Multi function Serial Interface 9
0001F4H 0001F8H 0001FCH 000200H 000204H 000208H 00020CH 000210H 000214H 000218H 00021CH 000220H 000224H 000228H to 00023CH 000240H
RDRA/TDRA [R/W] * ISMKA [R/W] * IBSAA [R/W] *
Multi function Serial Interface 10
DMAC
Reserved
DMAC (Continued) 43
MB91345 Series
Address 000244H to 0003BCH 0003A0H 0003A4H 0003A8H 0003ACH 0003B0H 0003B4H to 0003ECH 0003F0H 0003F4H 0003F8H 0003FCH 000400H 000404H 000408H 00040CH 000410H 000414H to 00041CH
Register 0 1 DATA_A [-/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DATA_B [-/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX MIN [R/W] 00000000 00000000 00000000 00000000 MAX [R/W] 00000000 00000000 00000000 00000000 ABS [R/W] 00000000 00000000 00000000 00000000 BSD0 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BSD1 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BSDC [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BSRR [R] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DDR0 [R/W] B, H DDR1 [R/W] B, H DDR2 [R/W] B, H DDR3 [R/W] B, H 00000000 00000000 00000000 00000000 DDR4 [R/W] B, H DDR5 [R/W] B, H DDR6 [R/W] B, H 00000000 00000000 ----0000 DDRC [R/W] B, H DDRD [R/W] B, H DDRE [R/W] B, H -----000 00000000 00000000 2 3
Block
Reserved
MIN/MAX/ABS
Reserved
Bit Search
Data Direction Registers
Reserved (Continued)
44
MB91345 Series
Address 000420H 000424H 000428H 00042CH 000430H 000434H to 00043CH 000440H 000444H 000448H 00044CH 000450H 000454H 000458H 00045CH 000460H 000464H 000468H 00046CH 000470H to 00047CH
Register 0 PFR0 [R/W] B, H 00000000 PFR4 [R/W] B, H 00000000 1 PFR1 [R/W] B, H 00000000 PFR5 [R/W] B, H 00000000 2 PFR2 [R/W] B, H 00000000 PFR6 [R/W] B, H ----0000 PFRC [R/W] B, H PFRD [R/W] B, H PFRE [R/W] B, H -----000 00000000 00000000 ICR00 [R, R/W] ---11111 ICR04 [R, R/W] ---11111 ICR08 [R, R/W] ---11111 ICR12 [R, R/W] ---11111 ICR16 [R, R/W] ---11111 ICR20 [R, R/W] ---11111 ICR24 [R, R/W] ---11111 ICR28 [R, R/W] ---11111 ICR32 [R, R/W] ---11111 ICR36 [R, R/W] ---11111 ICR40 [R, R/W] ---11111 ICR44 [R, R/W] ---11111 ICR01 [R, R/W] ---11111 ICR05 [R, R/W] ---11111 ICR09 [R, R/W] ---11111 ICR13 [R, R/W] ---11111 ICR17 [R, R/W] ---11111 ICR21 [R, R/W] ---11111 ICR25 [R, R/W] ---11111 ICR29 [R, R/W] ---11111 ICR33 [R, R/W] ---11111 ICR37 [R, R/W] ---11111 ICR41 [R, R/W] ---11111 ICR45 [R, R/W] ---11111 ICR02 [R, R/W] ---11111 ICR06 [R, R/W] ---11111 ICR10 [R, R/W] ---11111 ICR14 [R, R/W] ---11111 ICR18 [R, R/W] ---11111 ICR22 [R, R/W] ---11111 ICR26 [R, R/W] ---11111 ICR30 [R, R/W] ---11111 ICR34 [R, R/W] ---11111 ICR38 [R, R/W] ---11111 ICR42 [R, R/W] ---11111 ICR46 [R, R/W] ---11111 ICR03 [R, R/W] ---11111 ICR07 [R, R/W] ---11111 ICR11 [R, R/W] ---11111 ICR15 [R, R/W] ---11111 ICR19 [R, R/W] ---11111 ICR23 [R, R/W] ---11111 ICR27 [R, R/W] ---11111 ICR31 [R, R/W] ---11111 ICR35 [R, R/W] ---11111 ICR39 [R, R/W] ---11111 ICR43 [R, R/W] ---11111 ICR47 [R, R/W] ---11111 3 PFR3 [R/W] B, H 00000000
Block
Registers
Reserved
Interrupt Control Unit
Reserved (Continued)
45
MB91345 Series
Address 000480H 000484H 000488H 00048CH 000490H 000494H to 0004FCH 000500H 000504H 000508H 00050CH 000510H 000514H to 00051CH 000520H
Register 0 RSRR [R, R/W] 10000000 CLKR [R/W] 00000000 OSCR [R/W] 00000000 OSCT [R/W] XXXXXXXX PCR0 [R/W] B, H PCR1 [R/W] B, H 00000000 00000000 PCR5 [R/W] B, H PCR6 [R/W] B, H 00000000 ----0000 PCRC [R/W] B, H PCRD [R/W] B, H PCRE [R/W] B, H -----000 00000000 00000000 EPFR0 [R/W] B, H 00000000 EPFR4 [R/W] B, H 11111111 EPFRC [R/W] B, H -----000 EPFR1 [R/W] B, H 00000000 EPFR5 [R/W] B, H 11111111 EPFRD [R/W] B, H 00000000 EPFRE [R/W] B, H 00000000 EPFR2 [R/W] B, H 11111111 EPFR6 [R/W] B, H ----1000 EPFR3 [R/W] B, H 11111111 1 STCR [R/W] 00110011 WPR [W] XXXXXXXX 2 TBCR [R/W] 00XXXX00 DIVR0 [R/W] 00000011 OSCCR [R/W] XXXXXXXX 3 CTBR [W] XXXXXXXX DIVR1 [R/W] 00000000
Block
Clock Control Unit
Reserved Stb. Wait Timer
Reserved
Port Pull-up Control Registers
Reserved
000524H 000528H 00052CH 000530H 000534H to 000550H
Extra Port Function Registers
Reserved (Continued)
46
MB91345 Series
Address 000554H 000558H 00055CH 000560H 000564H to 000574H 000578H 00057CH to 00063CH 000640H 000644H 000648H 00064CH 000650H 000654H to 00065CH 000660H 000664H 000668H to 00067CH 000680H 000684H 000688H to 0007F8H
Register 0 TTCR0 [R/W] B, H, W 11110000 1 2 3 TSTPR0 [R] B, H, W 00000000
Block
COMP0 [R/W] COMP2 [R/W] COMP4 [R/W] COMP6 [R/W] B, H, W 00000000 B, H, W 00000000 B, H, W 00000000 B, H, W 00000000 TTCR1 [R/W] B, H, W 11110000 TSTPR1 [R] B, H, W 00000000
Timing Generator
COMP8 [R/W] COMP10 [R/W] COMP12 [R/W] COMP14 [R/W] B, H, W 00000000 B, H, W 00000000 B, H, W 00000000 B, H, W 00000000 ADTGS [R/W] B ------00 ASR0 [R/W] 00000000 00000000 ASR1 [R/W] 00000000 XXXXXXXX ASR2 [R/W] XXXXXXXX XXXXXXXX ASR3 [R/W] 00000000 XXXXXXXX T-Unit AWR0 [R/W] B, H, W 01111111 11111111 AWR2 [R/W] B, H, W XXXXXXXX XXXXXXXX CSER [R/W] B, H, W 00000001 TCR [W] B, H, W 0000XXXX AWR1 [R/W] B, H, W XXXXXXXX XXXXXXXX AWR3 [R/W] B, H, W XXXXXXXX XXXXXXXX ACR0 [R/W] 00110X00 00000000 ACR1 [R/W] 0XXX0X00 00X0XXXX ACR2 [R/W] XXXX0X00 00X0XXXX ACR3 [R/W] 01XX0X00 00X0XXXX Reserved
AD Trigger Select
Reserved

Not Used (Continued) 47
MB91345 Series
Address 0007FCH 000800H to 000AFCH 000B00H 000B04H 000B08H
Register 0 1 MODR [W] XXXXXXXX ESTS0 [R/W] B X0000000 ECTL0 [R/W] B 0X000000 ECNT0 [W] B XXXXXXXX ESTS1 [R/W] B XXXXXXXX ECTL1 [R/W] B 00000000 ECNT1 [W] B XXXXXXXX ESTS2 [R] B 1XXXXXXX ECTL2 [W] B 000X0000 EUSA [W] B XXX00000 ECTL4 [R] ([R/W]) B -0X00000 ECTL3 [R/W] B 00X00X11 EDTC [W] B 0000XXXX ECTL5 [R] ([R/W]) B ----000X 2 3
Block Not Used
000B0CH
EWPT [R] H 00000000 00000000 EDTR0 [W] H XXXXXXXX XXXXXXXX
000B10H 000B14H to 000B1CH 000B20H 000B24H 000B28H 000B2CH 000B30H 000B34H 000B38H 000B3CH 000B40H 000B44H 000B48H
EDTR1 [W] H XXXXXXXX XXXXXXXX
EIA0 [W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EIA1 [W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EIA2 [W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EIA3 [W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EIA4 [W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EIA5 [W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EIA6 [W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EIA7 [W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EDTA [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EDTM [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EOA0 [W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX (Continued) DSU (Evaluation Chip Only)
48
MB91345 Series
Address 000B4CH 000B50H 000B54H 000B58H 000B5CH 000B60H 000B64H 000B68H 000B6CH 000B70H to 000FFCH 001000H 001004H 001008H 00100CH 001010H 001014H 001018H 00101CH 001020H 001024H 001028H to 006FFCH
Register 0 1 2 3 EOA1 [W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EPCR [R/W] W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EPSR [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EIAM0 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EIAM1 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EOAM0/EODM0 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EOAM1/EODM1 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EOD0 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EOD1 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMASA0 [R/W] 00000000 00000000 00000000 00000000 DMADA0 [R/W] 00000000 00000000 00000000 00000000 DMASA1 [R/W] 00000000 00000000 00000000 00000000 DMADA1 [R/W] 00000000 00000000 00000000 00000000 DMASA2 [R/W] 00000000 00000000 00000000 00000000 DMADA2 [R/W] 00000000 00000000 00000000 00000000 DMASA3 [R/W] 00000000 00000000 00000000 00000000 DMADA3 [R/W] 00000000 00000000 00000000 00000000 DMASA4 [R/W] 00000000 00000000 00000000 00000000 DMADA4 [R/W] 00000000 00000000 00000000 00000000
Block
DSU (Evaluation Chip Only)
Reserved
DMAC
Reserved (Continued) 49
MB91345 Series
(Continued) Address 007000H 007004H 007008H to 007019H 007020H 007024H to 00702CH 007030H 007034H 007038H 00703CH 007040H 007044H 007048H 00704CH 007050H 007054H 007058H 00705CH 007060H 007064H 007068H 00706CH WREN [R/W] 00000000 WA0 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX WD0 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX WA1 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX WD1 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX WA2 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX WD2 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX WA3 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX WD3 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX WA4 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX WD4 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX WA5 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX WD5 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX WA6 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX WD6 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX WA7 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX WD7 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX Register 0 FLCR [R/W] 01101000 FLWC [R/W] 00110011 Reserved 1 2 Flash Interface 3 Block
Flash Interface
Flash Interface
* : Refer to "Hardware manual" for initial value. 50
MB91345 Series
VECTOR TABLE
Interrupt No. Interrupt factor Reset Mode vector System reserved System reserved System reserved System reserved System reserved Coprocessor absent trap Coprocessor error trap INTE instruction Instruction break exception Operand break trap Step trace trap NMI request (tool) Undefined instruction exception NMI request External interrupt 0 External interrupt 1 External interrupt 2 External interrupt 3 External interrupt 4 External interrupt 5 External interrupt 6 External interrupt 7 Reload timer 0 Reload timer 1 Reload timer 2 UART0 RX/I C0 status UART0 TX UART1 RX/I C1 status UART1 TX UART2 RX/I2C2 status UART2 TX
2 2
HexaDecimal decimal
Interrupt Offset level 15 (FH) fixed ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 ICR07 ICR08 ICR09 ICR10 ICR11 ICR12 ICR13 ICR14 ICR15 ICR16 3FCH 3F8H 3F4H 3F0H 3ECH 3E8H 3E4H 3E0H 3DCH 3D8H 3D4H 3D0H 3CCH 3C8H 3C4H 3C0H 3BCH 3B8H 3B4H 3B0H 3ACH 3A8H 3A4H 3A0H 39CH 398H 394H 390H 38CH 388H 384H 380H 37CH
Address of TBR default 000FFFFCH 000FFFF8H 000FFFF4H 000FFFF0H 000FFFECH 000FFFE8H 000FFFE4H 000FFFE0H 000FFFDCH 000FFFD8H 000FFFD4H 000FFFD0H 000FFFCCH 000FFFC8H 000FFFC4H 000FFFC0H 000FFFBCH 000FFFB8H 000FFFB4H 000FFFB0H 000FFFACH 000FFFA8H 000FFFA4H 000FFFA0H 000FFF9CH 000FFF98H 000FFF94H 000FFF90H 000FFF8CH 000FFF88H 000FFF84H 000FFF80H 000FFF7CH
DMA transfer
DMAC STOP factor
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20
STOP STOP STOP
(Continued) 51
MB91345 Series
Interrupt No. Interrupt factor UART3 RX/TX/SX UART4 RX/TX/SX UART5 RX/TX/SX UART6 RX/TX/SX UART7 RX/TX/SX UART8 RX/TX/SX UART9 RX/TX/SX UART10 RX/TX/SX A/D Converter 0 A/D Converter 1 PWC (measurement completed, overflow) System reserved Up/Down Counter 1 Up/Down Counter 2, 3 Timebase Timer Overflow PPG 0/PPG 1/PPG 4/PPG 5 PPG 2/PPG 3/PPG 6/PPG 7 PPG 8/PPG 9/PPG C/PPG D PPG A/PPG B/PPG E/PPG F Free Running Timer 0 Free Running Timer 1 Input Capture 0/ Input Capture 1/ Input Capture 2/ Input Capture 3 Input Capture 4/ Input Capture 5/ Input Capture 6/ Input Capture 7 Output Compare 0/ Output Compare 1/ Output Compare 2/ Output Compare 3 Output Compare 4/ Output Compare 5/ Output Compare 6/ Output Compare 7
HexaDecimal decimal
Interrupt level ICR17 ICR18 ICR19 ICR20 ICR21 ICR22 ICR23 ICR24 ICR25 ICR26 ICR27 ICR28 ICR29 ICR30 ICR31 ICR32 ICR33 ICR34 ICR35 ICR36 ICR37
Offset 378H 374H 370H 36CH 368H 364H 360H 35CH 358H 354H 350H 34CH 348H 344H 340H 33CH 338H 334H 330H 32CH 328H
Address of TBR default 000FFF78H 000FFF74H 000FFF70H 000FFF6CH 000FFF68H 000FFF64H 000FFF60H 000FFF5CH 000FFF58H 000FFF54H 000FFF50H 000FFF4CH 000FFF48H 000FFF44H 000FFF40H 000FFF3CH 000FFF38H 000FFF34H 000FFF30H 000FFF2CH 000FFF28H
DMA DMAC transfer STOP factor
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35

54
36
ICR38
324H
000FFF24H
55
37
ICR39
320H
000FFF20H
56
38
ICR40
31CH
000FFF1CH
57
39
ICR41
318H
000FFF18H
(Continued)
52
MB91345 Series
(Continued) Interrupt No. Interrupt factor System reserved External interrupt 8 to External interrupt 15 External interrupt 16 to External interrupt 23 Up/Down Counter 0 DMA (0 channel to 4 channels) Delayed interrupt activation System reserved (Used by REALOS) System reserved (Used by REALOS) System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved Used by INT instruction
Decimal Hexadecimal
Interrupt level ICR42 ICR43 ICR44 ICR45 ICR46 ICR47
Offset 314H 310H 30CH 308H 304H 300H 2FCH 2F8H 2F4H 2F0H 2ECH 2E8H 2E4H 2E0H 2DCH 2D8H 2D4H 2D0H 2CCH 2C8H 2C4H 2C0H 2BCH to 000H
Address of TBR default 000FFF14H 000FFF10H 000FFF0CH 000FFF08H 000FFF04H 000FFF00H 000FFEFCH 000FFEF8H 000FFEF4H 000FFEF0H 000FFEECH 000FFEE8H 000FFEE4H 000FFEE0H 000FFEDCH 000FFED8H 000FFED4H 000FFED0H 000FFECCH 000FFEC8H 000FFEC4H 000FFEC0H 000FFEBCH to 000FFC00H
DMA DMAC transfer STOP factor
58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 to 255
3A 3B 3C 3D 3E 3F 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 to FF
53
MB91345 Series
ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Rating
Parameter Power supply voltage * Analog power supply voltage * Input voltage * Analog pin input voltage * Storage temperature Symbol VCC AVCC VI VIA Tstg Rating Min VSS-0.5 VSS-0.3 VSS-0.3 VSS-0.3 -40 Max VSS + 4.0 VSS + 4.0 VSS + 4.0 AVcc + 0.5 +125 Unit V V V V C
* : The parameter is based on VSS = AVSS = 0.0 V. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
2. Recommended Operating Conditions
(VSS = AVSS = 0) Parameter Operating temperature Power supply voltage Analog power supply voltage Symbol Ta VCC AVCC Value Min - 40 3.0 3.0 Max + 85 3.6 VCC Unit C V V
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand.
54
MB91345 Series
3. DC Characteristics
Parameter Symbol Pin (VCC = AVCC = 3.0 V to 3.6 V, VSS = AVSS = 0 V, Ta = -40 C to + 85 C) Conditions During normal operation Ta = + 25 C fcp = 50 MHz, fcpp = 25 MHz SLEEP mode during normal operation Ta = + 25 C fcp = 50 MHz, fcpp = 25 MHz In STOP mode Ta = + 25 C, fclk = 0 In STOP mode Ta = + 45 C, fclk = 0 Value Min Typ Max Unit Remarks
ICC
65
80
mA
Power supply current
ICCS
VCC
30
35
mA
66
390
A
ICCH
140
760
A P20 to P27, P30 to P37, P40 to P47 P20 to P27, P30 to P37, P40 to P47
"H" level input voltage "L" level input voltage "H" level input voltage "L" level input voltage "H" level output voltage "L" level output voltage Input leak current A/D power supply current (analog + digital)
VIH
VCC x 0.7
VCC
V
VIL VIH VIL VOH VOL IIL

IOH = -4 mA IOL = 4 mA
VSS VCC x 0.8 VSS VCC - 0.5 VSS -5
7.2
VCC x 0.3 VCC VCC x 0.2 VCC 0.4 +5 5
V V V V V A mA A
At operating A/D 2 unit At power down operation* At operating A/D 2 unit AVRH = 3.0 V, VSS = 0.0 V At power down operation*
A/D reference power supply current (AVRH to VSS)

940
A

10
A
* : Current when A/D converter is not operating and the CPU is in stop mode.
55
MB91345 Series
4. AC Characteristics
(1) Main Clock Input Standard (VCC = AVCC = 3.0 V to 3.6 V, VSS = AVSS = 0 V, Ta = -40 C to + 85 C) Parameter Clock frequency Input clock cycle Input clock pulse width Input clock rise time and fall time Internal operating clock frequency Peripheral clock cycle time Symbol fC tCYL tCF tCR fCP X0 Pin Conditions PWH/tCYL PWL/tCYL 40 Value Min Typ 12.5 80 60 5 50 Max Unit MHz ns % ns In external clock Remarks
MHz CPU core operation clock Peripheral clock is derived from internal operating clock divided by 1/1 to 1/16.
tCYCP
30
ns
tCYL
0.8 x VCC
0.8 x VCC VSS + 0.4 PWH tCF PWL tCR
0.8 x VCC VSS + 0.4
X0
56
MB91345 Series
(2) PLL Oscillation Stabilization Wait Time (LOCK UP Time) (VCC = AVCC = 3.0 V to 3.6 V, VSS = AVSS = 0 V, Ta = -40 C to + 85 C) Parameter PLL oscillation stabilization wait time (LOCK UP time) Symbol tLOCK Value Min 500 Max Unit s Remarks Wait time until the PLL oscillation is stable.
(3) Reset Input Standard (VCC = AVCC = 3.0 V to 3.6 V, VSS = AVSS = 0 V, Ta = -40 C to + 85 C) Parameter Reset input time (except power-on) Symbol tINTL Pin INIT Conditions Value Min tCP x 10 Max Unit ns Remarks
Notes : * tCP is cycle time for CPU operation clock (CLKB) . * For power-on, input INIT = "L" more than regulator voltage stabilization wait time. If the oscillation stabilization wait time of used oscillator takes more time than regulator voltage stabilization wait time, input INIT = "L" until the oscillation is stable.
tINTL
INIT
VIL VIL
57
MB91345 Series
(4) UART Timing (VCC = AVCC = 3.0 V to 3.6 V, VSS = AVSS = 0 V, Ta = -40 C to + 85 C) Parameter Serial clock cycle time SCK SOT delay time Valid SIN SCK SCK valid SIN hold time Serial clock "H" pulse width Serial clock "L" pulse width SCK SOT delay time Valid SIN SCK SCK valid SIN hold time Symbol tSCYC tSLOV tIVSH tSHIX tSHSL tSLSH tSLOV tIVSH tSHIX Pin SCK0 to SCK10 SCK0 to SCK10, SOT0 to SOT10 SCK0 to SCK10, SIN0 to SIN10 SCK0 to SCK10, SIN0 to SIN10 SCK0 to SCK10 SCK0 to SCK10 SCK0 to SCK10, External shift SOT0 to SOT10 clock SCK0 to SCK10, operation SIN0 to SIN10 SCK0 to SCK10, SIN0 to SIN10 Internal shift clock operation Conditions Value Min 4 tCYCP - 20 30 20 2 tCYCP 2 tCYCP 20 20 Max + 20 30 Unit ns ns ns ns ns ns ns ns ns
Notes : * AC rating in CLK synchronous mode * tCYCP is the peripheral clock cycle time.
58
MB91345 Series
* Internal shift clock mode
tSCYC VOH VOL tSLOV VOL
SCK0 to SCK10
SOT0 to SOT10
VOH VOL tIVSH VOH VOL tSHIX VOH VOL
SIN0 to SIN10
* External shift clock mode
tSLSH tSHSL VOH VOL tSLOV VOL VOH
SCK0 to SCK10
SOT0 to SOT10
VOH VOL tIVSH tSHIX VOH VOL
SIN0 to SIN10
VOH VOL
59
MB91345 Series
(5) Free-run timer clock, Reload timer event Input , up down counter Input , Input capture Input, Interrupt Input Timing (VCC = AVCC = 3.0 V to 3.6 V, VSS = AVSS = 0 V, Ta = -40 C to + 85 C) Parameter Symbol Pin FRCK0, FRCK1, TIN0, TIN1, TIN2, IC0, IC1, AIN0, AIN1, BIN0, BIN1, ZIN0, ZIN1 INT0 to INT23 *1 : tCYCP is cycle time for peripheral clock. *2 : Except in stop time *3 : In stop time Conditions Value Min Max Unit Remarks
tCYCP x 2 tCYCP x 3 1.0
ns
*1
Input pulse width
tTIWH tTIWL

ns s
*2 *3
FRCK0, FRCK1, TIN0, TIN1, TIN2, IC0, IC1, AIN0, AIN1, BIN0, BIN1, ZIN0, ZIN1, INT0 to INT23
tTIWH VIH VIL VIL
tTIWL VIH
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MB91345 Series
(6) A/D Trigger Input Timing (VCC = AVCC = 3.0 V to 3.6 V, VSS = AVSS = 0 V, Ta = -40 C to + 85 C) Parameter Symbol Pin Conditions Value Min tCYCP x 2 Max Unit Remarks
A/D trigger input (falling time)
ADTRG0, ADTRG0-2, tTADTG ADTRG1, ADTRG1-2
ns
*
* : tCYCP is the peripheral clock cycle time.
tTADTG ADTRG0, ADTRG0-2, ADTRG1, ADTRG1-2 VIL VIL VIH
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MB91345 Series
(7) I2C timing * At master mode operating
(VCC = AVCC = 3.0 V to 3.6 V, VSS = AVSS = 0 V, Ta = -40 C to + 85 C) Conditions Typical mode Min Max 100 5 x M*1 High-speed mode*3 Min 0 1.3 0.6 Max 400 5 x M*1 kHz s s ns Unit Remarks
Parameter SCL clock frequency "L" period of SCL clock "H" period of SCL clock SCL SDA output delay time Bus free time between [STOP condition] and [START condition] SDA data input hold time (vs. SCL) SDA data input setup time (vs. SCL) Setup time of [repeat START condition] SCL SDA Hold time of [repeat START condition] SDA SCL Setup time of [STOP condition] SCL SDA
Symbol fSCL tLOW tHIGH tDLDAT
0 4.7 4.0
tBUS
4.7
1.3
s
tHDDAT tSUDAT
R = 1 k C = 50 pF*4
2 x M*1 250

2 x M*1 100*2

s ns
tSUSTA
4.7
0.6
s After that, the first clock pulse is generated.
tHDSTA
4.0
0.6
s
tSUSTO
4.0
0.6
s
*1 : M = Resource clock cycle (ns) *2 : A high-speed mode I2C bus device can be used for a typical mode I2C bus system as long as the device satisfies a requirement of "tSUDAT 250 ns". When a device does not extend the "L" period of the SCL signal, the next data must be outputted to the SDA line within 1250 ns (maximum SDA/SCL rise time + tSUDAT) in which the SCL line is released. *3 : For use at over 100 kHz, set the resource clock to at least 6 MHz. *4 : R and C represent the pull-up resistor and load capacitor of the SCL and SDA output lines, respectively.
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MB91345 Series
* At slave mode operating (VCC = AVCC = 3.0 V to 3.6 V, VSS = AVSS = 0 V, Ta = -40 C to + 85 C) Parameter SCL clock frequency "L" period of SCL clock "H" period of SCL clock SCL SDA output delay time Bus free time between [STOP condition and START condition] SDA data input hold time (vs. SCL) SDA data input setup time (vs. SCL) Setup time of [repeat START condition] SCL SDA Hold time of [repeat START condition] SDA SCL Setup time of [STOP condition] SCL SDA Symbol fSCL tLOW tHIGH tDLDAT Conditions Typical mode Min 0 4.7 4.0 Max 100 5 x M*1 High-speed mode*3 Min 0 1.3 0.6 Max 400 5 x M*1 kHz s s ns Unit Remarks
tBUS R = 1 k C = 50 pF*4
4.7
1.3
s
tHDDAT tSUDAT
2 x M*1 250

2 x M*1 100*2

s ns s After that, the first clock pulse is generated.
tSUSTA
4.7
0.6
tHDSTA
4.0
0.6
s
tSUSTO
4.0
0.6
s
*1 : M = Resource clock cycle (ns) *2 : A high-speed mode I2C bus device can be used for a typical mode I2C bus system as long as the device satisfies a requirement of "tSUDAT 250 ns". When the device does not extend the "L" period of the SCL signal, the next data must be outputted to the SDA line within 1250 ns (maximum SDA/SCL rise time + tSUDAT) in which the SCL line is released. *3 : For use at over 100 kHz, set the resource clock to at least 6 MHz. *4 : R and C represent the pull-up resistor and load capacitor of the SCL and SDA output lines, respectively.
63
MB91345 Series
(8) Regulator Voltage Wait Time (VCC = AVCC = 3.0 V to 3.6 V, VSS = AVSS = 0 V, Ta = -40 C to + 85 C) Parameter Regulator voltage wait time Symbol tREG Value Min 250 Max Unit s Remarks Wait time until the regulator voltage is stable
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MB91345 Series
5. Electrical Characteristics for the A/D Converter
(VCC = AVCC = 3.0 V to 3.6 V, VSS = AVSS = 0 V, AVRH = 3.0 V to 3.6 V, Ta = -40 C to + 85 C) Parameter Resolution Total error*
1
Value Min -3.0 -2.5 -1.9 -1.5 AVRH-3.5 0.6 0.3*3 0.9*
3
Typ +0.5 AVRH-1.5 1.1 7.2 940
Max 10 +3.0 +2.5 +1.9 +2.5 AVRH+0.5 5 10 20 4
Unit bit LSB LSB LSB LSB LSB s s s mA A A A pF LSB
Remarks
Nonlinear error*1 Differential linear error*1 Zero transition voltage*1 Full transition voltage*
1
AVCC = 3.3 V, AVRH = 3.3 V
Minimum comparison time*2 Minimum sampling time*2 Conversion time Power supply current (analog + digital) Reference power supply current (between AVRH and AVRL) Analog input capacitance Interchannel disparity
Not including sampling time
At operating A/D 2 unit At power down operation*4 At operating A/D 2 unit AVRH = 3.0 V, AVRL = 0.0 V At power down operation*4
*1 : Measured in the CPU sleep state. *2 : Depends on the clock cycle supplied to the peripheral resource. *3 : No external load *4 : Current when the A/D converter is not operating and the CPU is in stop mode
65
MB91345 Series
* About the external impedance of the analog input and its sampling time * A/D converter with sample and hold circuit. If the external impedance is too high to keep sufficient sampling time, the analog voltage charged to the internal sampling and hold capacitor is insufficient, adversely affecting A/D conversion precision. Therefore, to satisfy the A/D conversion precision standard, consider the relationship between the external impedance and minimum sampling time and either adjust the resistor value and operating frequency or decrease the external impedance so that the sampling time is longer than the minimum value. If the sampling time cannot be sufficient, connect a capacitor of about 0.1 F to the analog input pin.
* Analog input circuit model
R
Analog input pin
C
Comparator
During sampling : ON R C 1.5 k (Max) 20.0 pF (Max)
Note : The values are reference values.
MB91F345B/F346B
* The relationship between the external impedance and minimum sampling time [External impedance = 0 k to 100 k]
100
[External impedance = 0 k to 20 k]
20
External impedance (k)
90 80 70 60 50 40 30 20 10 0 0 5 10 15 20 25 30 35
External impedance (k)
18 16 14 12 10 8 6 4 2 0 0 1 2 3 4 5 6 7 8
Minimum sampling time (s)
Minimum sampling time (s)
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MB91345 Series
* A/D Converter Block Electrical Characteristics * Resolution Analog variations recognized by an A/D converter. * Linearity error Deviation of actual conversion characteristics from an ideal line, which is across zero-transition point ("00 0000 0000" "00 0000 0001") and full-scale transition point ("11 1111 1110" "11 1111 1111"). * Differential linearity error Deviation from ideal value of input voltage, which is required for changing output code by 1 LSB. * Total error Difference between actual value and ideal value. The error includes zero-transition error, full-scale transition error, and linearity error.
Total error
3FFH 3FEH 3FDH
Actual characteristic
{1 LSB' (N - 1) + 0.5 LSB'}
1.5 LSB'
Digital output
004H 003H 002H 001H
(Actual measured value)
VNT
Actual characteristic Ideal characteristics
0.5 LSB'
AVSS
Analog input
AVRH
1 LSB' (ideal value) =
AVRH - AVSS [V] 1024 VNT - {1 LSB' x (N - 1) + 0.5 LSB'} Total error of digital output N = 1 LSB'
VNT : Transition voltage for digital output to change from (N + 1) H to NH. VOT' (ideal value) = AVSS + 0.5 LSB' [V] VFST' (ideal value) = AVRH - 1.5 LSB' [V] (Continued)
67
MB91345 Series
(Continued) Linearity error
3FFH 3FEH 3FDH
Differential linearity error
Actual conversion characteristic
N + 1H
Actual conversion characteristic
{1 LSB' (N - 1) + VOT}
VFST Digital output
(Actual measured value)
Digital output
NH
Ideal characteristics
004H 003H 002H 001H
VNT
(Actual measured value)
VFST
N - 1H
(Actual measured value)
Actual conversion characteristic Ideal characteristics
VNT
(Actual measured value)
VOT (Actual measured value)
AVSS
N - 2H
Actual conversion characteristic
Analog input
AVRH
AVSS
Analog input
AVRH
Linearity error of digital output N =
VNT - {1 LSB' x (N - 1) + VOT} [LSB] 1 LSB' V (N+1) T - VNT Differential linearity error of digital output N = -1[LSB] 1 LSB' VFST - VOT 1 LSB = [V] 1022
VOT : Transition voltage for digital output to change from (000) H to (001) H. VFST : Transition voltage for digital output to change from (3FE) H to (3FF) H.
* About errors * As |AVRH - AVSS| becomes smaller, values of relative errors grow larger.
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MB91345 Series
6. Flash Memory Write/Erase Characteristics
(VCC = AVCC = 3.0 V to 3.6 V, VSS = AVSS = 0 V, Ta = - 40 C to + 85 C) Parameter Sector erase time Byte write time Chip write time Erase/write cycle Flash memory data retain period Conditions Average Ta = + 55 C Value Min 10000 10 Typ 1 6 3.4 Max 15 100 56 Unit s s s cycle year * Remarks Excludes 00H programming prior erasure Not including system-level overhead time Not including system-level overhead time
* : This value comes from the technology qualification (using Arrhenius equation to translate high temperature measurements into normalized value at + 55 C) .
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MB91345 Series
ORDERING INFORMATION
Part number MB91F345BPFT-GE1 MB91F346BPFT-GE1 Package 100-pin plastic TQFP (FPT-100P-M18)
70
MB91345 Series
PACKAGE DIMENSIONS
100-pin plastic TQFP Lead pitch Package width x package length Lead shape Sealing method Mounting height Weight 0.40 mm 12.0 x 12.0 mm Gullwing Plastic mold 1.20 mm MAX 0.40g P-TFQFP100-12 x 12-0.40
(FPT-100P-M18)
Code(Reference)
100-pin plastic TQFP (FPT-100P-M18)
14.000.20(.551.008)SQ * 12.000.10(.472.004)SQ
75 51
Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder.
0.1450.055 (.006.002)
76
50
0.08(.003)
Details of "A" part 1.100.10 (.043.004) INDEX
100 26
0~8 "A"
0.100.05 (.004.002) (Stand off)
0.25(.010) LEAD No.
1 25
0.600.15 (.024.006) 0.07(.002)
M
0.40(.016)
0.180.05 (.007.002)
C
2003 FUJITSU LIMITED F100029S-c-3-4
Dimensions in mm (inches). Note: The values in parentheses are reference values.
Please confirm the latest Package dimension by following URL. http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.html
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MB91345 Series
The information for microcontroller supports is shown in the following homepage. http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html
FUJITSU LIMITED
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of Fujitsu or any third party or does Fujitsu warrant non-infringement of any third-party's intellectual property right or other right by using such information. Fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan. The company names and brand names herein are the trademarks or registered trademarks of their respective owners. Edited Business Promotion Dept.
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